DATA ACQUISITION SYSTEM
CAMAC based instrumentation system is used for acquiring data and an interrupt driven software is used for recording data. The rates of 49 photo-tube's and 7 telescope's pulses are monitored continuously and recorded at regular intervals using monitoring interrupts of frequency 1 Hz. Event interrupt due to the presence of Event trigger initiates data recording and is given the highest priority. The event data consists of relative arrival time of Cherenkov shower front at each mirror accurate to 0.25 ns as measured by TDCs, Cherenkov photon density at each mirror using 12 bit QDC, absolute arrival time of event accurate to 0.25ns as given by Real Time Clock (RTC) module synchronized with GPS and other informations like the triggered telescopes in an event.
block diagram circuit diagram
CAMAC controller is an interface between the CAMAC modules and computer. The main task of the controller is to interpret the computer commands and execute the corresponding CAMAC commands on the addressed module.
The controller has two cards : controller -A and controller -B.
The controller -A decodes the camac commands from I/O card and initiates a CAMAC cycle routing the command, address and control signals to CAMAC bus. It also writes data to or reads data from the CAMAC bus via controller-B during CAMAC cycle.
The controller-B also accommodates an independent controller utility module which supports several functionalities useful for the DAQ system.
Every CAMAC command initiates a CAMAC cycle.The final LAM is generated from the individual unmasked LAM's.This LAM optionally invokes interrupt INT1. This module supports two front panel NIM triggers 0,1 which invokes INT0 & INT1 repectively.NIM bar n VETO - 0 & 1 at front panel active at trailing edge of respective TRIG. input triggers and made inactive by the software at the end of interrupt routine.Control/Status section initializes and controls functionalities of different sections of the card.
CAMAC cycle is initiated by any one of CAMAC command, SW repeat command, (-SREP), Hardware repeat command (when set by control section, repeats n times set inthe cycle counter, with subsequent increase in sub address A and station address N) and Fast CAMAC repeat command ( S1 section of CAMAC cycle repeats till cycle counter reaches to zero.)
Supports all camac functions.
Supports two front panel NIM triggers invoking two interrupts on ISA bus and generates respective busy signal vide n VETO(NIM_BAR) on front panel.
The LAM on the selected modules also invoke the second interrupt of the two interrupts mentioned above.The LAM flags corresponding to 24 CAMAC slots can be read through 24-bit LAM register.
A software controlled NIM std output is provided at the front panel.
CAMAC commands can be repeated incrementing sub address and station address using SW controlled signal while reading data.
CAMAC command can be repeated by preset no. of times in hardware mode.
Supports FAST CAMAC cycles for repeated by command.
CAMAC address and funtion codes are displayed to the user using LED's.
By enabling buffer mode recording of controller-b one can record 16 - bit data from the CAMAC bus into FIFO buffer in hardware to reduce the interrupt processing time ( dead time) .The data can be read from FIFO later in the main program.
Self diagnosis features.
This is a CAMAC module designed as a data card with utility functions for self diagnosis as well as for typical DAQ applications.It has following sections:
1.Control Status REG
The CAMAC data bus vide W and R bus form a common 24-bit I/O bus connecting all above sections.
1.Control Status REG.
Control Status Register controls teh functions of different sesctions and status register reads status flags set by these sections.
control reg CR-16 Addr. D3...D0: 0 to 15] ,D4=1 signals set to active else inactive state.
Status Reg. 8-bit
It is a 24-bit presetable up-counter with clear , clock input,Gate and over flow.
This basic counter with control circuits supports following applications:
24-bit Read/Write Register: 24 bit data can be written and read. it can be used for diagnosis of CAMAC dataway.
steps: clear CR-16,write 24-bit data, Load to counter, Read data.
24-bit Scaler; It supports external GATE or SW GATE.It supports inhibit counting on overflow.Accepts input from front panel or SW counts.
steps: clear CR-16, Read data.
Pulse width measurement:
width of a NIM pulse given as GATE can be measured with a selected resolution out of 200ns, 400 ns, 800ns, 1600ns,external and dynamic range of 24-bit.
Clear CR-16, set: Resolution using FS1,FS0,set:OSC En, OF En,Clear counter,Allow pulse to be measured as Gate, Read data.
Signal generator: It can generate SW or HW programmable periodic NIM and tail pulse signals.
Hardware: Select the basic Clock freq using FS1,FS0
Set OSc En,PG En,n O/P En
Write &Load counter with a proper data to get a pulse on overflow.
Start PG activating nSW En.
Software: Activate nO/PEn
Activate/Deactivate nSWPG at desired frequency.
FIFO Buffer :
It is a 16-bit 4K FIFO buffer . It invokes LAM on half full or full flaf is active.EF-empty flag onto Q indicates data status in FIFO.It has Retransmit facility and Initialization of pointers to zero.some of the applications are:
dataway check: different patterns of 16 bit data can be written to FIFO and can be verified by reading back.
Pre-written standard data patterns can be read from FIFO on every calibration trigger to make sure CAMAC data operations.
Data logger: It is a 16-bit data logger which records data from GPIO in input mode at regular intervals decided by SW or external Strobe.
Fast Data Recorder: The 16-bit data from CAMAC read lines R1-R16 are recorded in FIFO on S1 of every CAMAC Read cycle performed on all modules.The data from FIFO can be read during idle period in main program.
General purpose I/O: I t is a 16-bit I/O to communicate with outside word with handshake signals like direction (D io/out) and strobe(nOSTB).Input data from external device is recorded into FIFO by External strobe (nISTB) or by SW.The data can be written to GPIO and can be read as check.