Paritosh K. Pandya : Home Page

(click here for the Formal Methods in India page.) (click here for the mu M Indian Classical Music project)

Paritosh K. Pandya
Associate Professor

Theoretical Computer Science Group
Tata Institute of Fundamental Research
Homi Bhabha Road, Colaba
Mumbai 400 005
India

phone:      (off)        + 91 22 2152971 ext 2551
                 (home)   + 91 22 2188725
                 (fax)       + 91 22 2152110

Email: pandya@tcs.tifr.res.in OR
pandya@tifr.res.in

My Curriculum Vitae and List of Publications are accessible in postscript form.

Research

Logic, Concurrency, Programming Languages, Formal Methods and Software Engineering.

Model checking
Duration Calculus and logics of Time
Refinement Algebra and CSP
Hoare Logics for Distributed Programs
Scheduling Theory

Tools

I have programmed DCVALID, a validity checker for Duration Calculus (QDDC) formulae. Chect it out!

COMING SOON Updated version 1.4 with the following. (See DCVALID page for preliminary documentation.)
      Extended logic called CTL[DC] enhancing QDDC with liveness and branching.
      Checks SMV designs using tool CTLDCSMV and SMV
      Checks Verilog designs using tool CTLDCVIS and VIS
      Checks Esterel designs using tool DCEST, Esterel Compiler and XEVE
      Checks SPIN (promella) designs using tool DCSPIN and SPIN.

Version 1.3 of DCVALID released on 10 August, 1999 comes with facilities for model checking ESTEREL, SMV or SPIN designs.
The Esterel checker DCEST has been documented.

Journal Editorial Board Membership

Formal Aspects of Computing , The international Journal of Formal Methods, Springer

Graduate Courses

Introduction to Logic (Aug-Dec 1999)

Model checking : Theory and Practice (Jan-Apr 1999)

Elementary Predicate Logic (Aug-Dec 1998, Aug-Dec 1996)

Science of Programming (Aug-Dec 1994)

Events

20th conference on Foundations of Software Technology and Theoretical Computer Science (FST&TCS 20), Delhi, India (13-15 December 2000).
sixth International Workshop and Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems (FTRTFT), Pune, India (20-22 September, 2000).
Advanced coure on RAISE and Duration Calculus, KIIT, Bhubaneshwar, (9-20 August, 1999).
IFIP WG 2.3 meeting at Technical University of Munich, Munich, Germany, (June, 1999).
BRNS workshop on Verification of Digital and Hybrid Systems (January, 1999).
FM'99 : World Congress on Formal Methods
IFIP WG 2.3 meeting at Indiana University, Bloomington, U.S.A. (June, 1998).
Esprit project ProCoS Kit workshop , Macau (May, 1998).
Eighth NSTCS , Bhubaneshwar, Orrisa, India (11-14 June 1998).
Advanced course on Specification and Verification of Real-time Systems using Duration Calculus

Course annoucement

plain text

postscript

FSTTCS17, Kharagpur (December 1997)
Course on Logical Foundations of Duration Calculus, UNU/IIST, Macau (October, 1997).
Update meeting on Reasoning about Timed Systems, IMSc, Chennai (June 1997)
Workshop on Applied Formal Methods, Hyderabad(December 1996)
Advanced course on Real-time Systems: Theory and Practice, NCST, Mumbai (November 1996)
IFIP WG 2.2 meeting in Macau (September 1996)
IFIP WG 2.2 Seminar in Beijing (November 1996)
Advanced course on Formal Methods in Software Development, SERC, IISc, Bangalore (April 1996)

Collaborators

Beyond Office

The mu M Project: Measuring Hidustani Classical Music.

Links

India Specific Search Engin
Mumbai (Bombay) information
Railway Time table (Beware: You must reserve seats in advance)

Last modified by Paritosh Pandya on 14 July 2000 August.