Details of Projects of national importance, done by myself, at TIFR, these were collaborative projects with multiple organizations:

1. Air Defense Ground Environment Systems (ADGES): This was initiated in 1969 by Dr. Vikram Sarabhai, Prof. M G K Menon et al with the active support from Mrs. Indira Gandhi, the then PM. It was strongly felt that India should generate know-how in the Defense Area and the Computer Group of TIFR was chosen as a Central Design and Development Centre with strong technical knowledge-base. Prof. P V S Rao was in-charge of this project from the start to finish (1969-1984), through all the phases of design and development. I was involved in this project from 1973-1984 (till the successful completion of the field model, connected with Live Radar, feeding Flying Aircraft data). From the publicly available data, it is known that 25 such systems were developed at the cost of Rs. 3 Crore each (in '80s) and have been deployed all over India, by the Indian Air Force. TIFR also helped ECIL and DAE to produce production version of these systems. Basic hardware, software, system design and development were completely done at TIFR. I was involved with the hardware and systems side of this project from 1973 onwards and was in-charge of these from 1979 till 1984, under the guidance of Prof. P V S Rao. We were co-recipient of VASVIK award for successful completion of this project. Prof. P V S Rao was awarded the PADMASREE in recognition. It is interesting to note that Tata Electric Company (Research and Development wing) co-developed the radar display units (along with ECIL) and later on these two companies (TEC & ECIL) were hugely active in Defense Systems development. The ADGES was a system consisting of three tightly-coupled computers (TDC 316: developed by BARC and then by ECIL) with 10-rackful of interface systems and 8 Display Units. It was used for running multiple complex modules of software for various control functions, under the overall control of an on-line Operating System. Multiple organizations: ECIL, Indian Air Force, Department of Electronics, Department of Atomic Energy, TIFR, were involved in this project, we being the central hub of this mammoth structure. The rugged version of the system was used heavily by the Indian Air Force. Thus, TIFR had been in a unique position of being a leader for the Indian Defense systems development, from early ’70 onwards. 
   
   Fall-out:  Biggest Electronic System built in the country at that time, multiple organizations were involved in the design and development of this project. Huge technical manpower training was provided. Development of Rugged System Design in India, when none were available from abroad. TIFR pioneered in all these activities. I had the unique advantage of working on this project for a long period from 1973 to 1984. 
   
2. Army Radio Engineering Network (AREN): I was involved in the development of the main processing unit of this system, the first microprogrammed computer, developed in India. This computer was the central control unit for the Mobile Electronic Telephone Exchange, being developed at TIFR under the guidance of Prof. P V S Rao and Prof. M V Pitke. This processor was developed using Bit-Slice Microprocessors (AMD Am 2901) and under the control of  60-bit Word Horizontal Microprogram of 512 words; basic design and development was done in a record time (from September 1, 1977 to December 27, 1977).  The NON-RESTORING DIVISION ALGORITHM, used in this Computer, was designed by me, and it was eventually used by IIT-Bombay in its IBM-370 emulation project and also by M/S MOTOROLA (USA) in their MC 6802 Microprocessor. The Dynamic Random Access Memory system used an Enhanced Version of Hamming Code, developed by me, which had Single Error Correcting  Hamming Code extended to detect Maximum possible Double Errors (without another parity bit). This part of the research work was also followed up in Rome, Italy. The rugged  version of the computer was used heavily by the Indian Army. TIFR again pioneered in developing this indigenous technology, thus providing a leading role for the technological development for the Indian Defense.
   
   Fall Out:  The know-how of this computer was passed on to the Department of Electronics, ECIL, ITI, Indian Army. Bharat Dynamics Limited (BDL) started a new department for producing a rugged version of this computer. M/S Tata Electric Company developed non-rugged version of this computer, these were heavily used at the Cyclone Warning Radar Centre at Chennai as the main processing unit. CDOT (Centre for Development of Telematics) was formed with a core group from TIFR, who were active in the development of the AREN project.
   
   These two project work (1) and (2) (1973-1984) was done under the oath of secrecy, whatever is being written here are only the publicly available data.
   

1. Single Error Correcting Partial Double Error Detecting Code : Single Error Correcting Partial Double Error Detecting (SEC-PDED) code having the same number of check-bits as the Hamming SEC Code was developed. This corrects all Single Bit Error and in addition detects a high fraction of all possible Double Errors (n-choose-2: for a (n,k) code where n is the sum of d data bits and k code bits. In other words, SEC-PDED corrects less number of false Single Errors than Hamming SEC Code. Extra hardware needed for this partial double error detection is minimal, a 10-input NAND gate for a (21, 16) SEC-PDED code. For a 60 bit machine (CDC Cyber 170), the PDED efficiency achieved is 90%+ with only 7 check bits. This code was implemented by Company Elettronica `MAEL’, Carsoli (Aquila), Italy for a computer memory system. (1978).
   
   Chronicled in the Reliability Information Analysis Center, Department of Defense, USA.URL:http://quanterion.com/RIAC/Library/Library.asp?ArgVal=14184-000
   
2. An Algorithm for Non-Restoring Division was developed. This published algorithm was used by M/S Motorola for their 6802 Microprocessor. This algorithm was also used in TIFR and in IIT, Mumbai for microprogrammed Processor design. (1977).
   
   A patent (US) was taken, Title: High speed digital divider having normalizing circuitry, United States Patent 4380051, by Inventor : Fette, Bruce A.
   
   URL: http://www.freepatentsonline.com/4380051.html, based on this work, sponsored by M/S Motorola, Inc. (Schaumburg, IL, USA)
   

1. 3-D Scanning Radar Attachment Project : Basic objective of this project was to produce a Computerized system which was connected to the 3-D Scanning Radars of the Cyclone Warning Radar Station of the Indian Meteorological Department at Madras (Chennai). The radar signal was pre-processed by Digital Video Integrating Processor (DVIP), designed and developed at TIFR. Output of the DVIP was fed to the processor, developed by me, for further processing and generation of “rainfall map” to be displayed on a video monitor. Some fall-outs of this project, partially under my supervision, are: [1978-1979] (a) Optimized Processor Design: In this model, circuit optimization and redistribution of functions were done, resulted in a processor with lower chip count (than the original design) and less input/output connections. (b) Dynamic Memory Design: A Dynamic Memory system was developed with Error Correction and Detection capability. (c ) Production version of the system: M/S Tata Electric Company developed two production version of this system, supervision effort was sought from me and complete guidance was provided.